发明名称 Testable bus control logic circuitry and method for using same
摘要 A bus control logic circuit is provided that may be tested for a variety of bus fault conditions including no-connection faults, cross-connection faults and bus-contention stuck faults. The bus control logic circuit operates in a normal mode and in a test mode. In the normal mode, the bus control logic circuit operates as a conventional driver decoder and is testable for no-connection faults and cross-connection faults. In the test mode, the bus control logic circuit also is testable for bus-contention stuck faults. To test for bus-contention stuck faults, drivers having addresses of a first parity are hard disabled and one of the hard disabled drivers is addressed. Because the addressed driver is hard disabled, the only driver that can be enabled is a non-addressed driver erroneously enabled due to a bus-contention stuck fault. To detect the bus-contention stuck fault, the signal line is placed in a known logic state that only changes if a driver is erroneously enabled due to a bus-contention stuck fault. Therefore, a change in the logic state of the signal line indicates the presence of a bus-contention stuck fault.
申请公布号 US6134682(A) 申请公布日期 2000.10.17
申请号 US19980143886 申请日期 1998.08.31
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 OAKLAND, STEVEN F.
分类号 G06F11/267;(IPC1-7):G11C29/00;G01R31/28 主分类号 G06F11/267
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