发明名称 |
Method for forming an integrated circuit |
摘要 |
In one embodiment, the reliability of an integrated circuit having a floating gate device (50), a high breakdown voltage transistor (52), and a low breakdown voltage transistor (54), which are electrically isolated from each other by a trench isolation region (12), is improved by using an oxidation resistant layer (24). The oxidation resistant layer (24) protects portions of the trench isolation region (12) when the gate dielectric layer (30) for the high breakdown voltage transistor (52) is formed, and when the gate dielectric layer (36) for the low breakdown voltage transistor (54) is formed. The oxidation resistant layer (24) minimizes etching of the field isolation region (12) so that thinning or recessing of the field isolation region (12) is minimized. |
申请公布号 |
US6133093(A) |
申请公布日期 |
2000.10.17 |
申请号 |
US19980015957 |
申请日期 |
1998.01.30 |
申请人 |
MOTOROLA, INC. |
发明人 |
PRINZ, ERWIN J.;YERIC, GREGORY M.;WU, KEVIN YUN-KANG;CHEN, WEI-MING;BAKER, FRANK KELSEY |
分类号 |
H01L21/8247;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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