发明名称 Redundancy method and a device for a non-volatile semiconductor memory
摘要 In a non-volatile semiconductor memory composed of floating gate field effect transistors arranged in rows and columns forming an array, a redundancy method is provided which includes the steps of: providing one or more column lines for redundancy, in which floating gate FETs in a number as many as the row lines of the array are connected; when a defect occurs in a column line, setting the thresholds of at least all the floating gate FETs connected to the defective column line, to the high state; and using as the substitute memory, the floating gate FETs for redundancy connected to redundancy column lines in a number as many as those of the floating gate FETs of which the thresholds are set in the high state.
申请公布号 US6134142(A) 申请公布日期 2000.10.17
申请号 US19990276776 申请日期 1999.03.25
申请人 SHARP KABUSHIKI KAISHA 发明人 HIRANO, YASUAKI
分类号 G11C16/04;G11C16/06;G11C29/04;H01L27/115;(IPC1-7):G11C16/06 主分类号 G11C16/04
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