| 摘要 |
PURPOSE: An improved data line layout structure of a semiconductor memory device is provided to realize the speedup of read operation. CONSTITUTION: An SRAM memory device includes a plurality of memory cell arrays formed in a block structure, block column pass sections, and block sense amplifiers. When data read from a cell array(100a) of a first block is outputted to the block sense amplifier(150a) through the block column pass section(130a), the block sense amplifier(150a) senses and amplifies a signal through a section data line. In particular, when the signal amplified in the block sense amplifier(150a) is transmitted to a main sense amplifier(200), transmission buses, i.e., main data lines(MDL), pass over a cell array(100n) of a second block. The main data lines(MDL) are formed with a metal layer different from that of a bit line or word line. Furthermore, the main data lines(MDL) have the same direction as the bit line has.
|
