发明名称 |
CLOCK SKEW MINIMIZATION SYSTEM AND METHOD FOR INTEGRATED CIRCUIT |
摘要 |
A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance. <IMAGE> |
申请公布号 |
KR100267430(B1) |
申请公布日期 |
2000.10.16 |
申请号 |
KR19970024459 |
申请日期 |
1997.06.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION. |
发明人 |
BOZSO, FERENC MIKLOS;EMMA, PHILIP GEORGE |
分类号 |
H01L21/60;G06F1/10;H01L23/52;H01L25/065;H01L25/07;H01L25/18;H01L27/02 |
主分类号 |
H01L21/60 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|