| 摘要 |
PURPOSE: An apparatus for transmitting and receiving data using a CPU peripheral bus for a switch is provided for integrating a plurality of buffers and resistors which form a CPU peripheral bus into one chip. CONSTITUTION: There are provided a CPU(100), a PLD(Programmable Logic Device)(110), a switching unit(120), a controller(130) and a memory unit(140). The CPU supplies data to the controller or supplies the data to the memory unit through the switching units. The PKD(20) generates a control signal in accordance with a corresponding address based on the address transmitted from the CPU through an address bus(IA) for thereby controlling the switching unit(120). The controller receives an address and data transmitted from the CPU through the address bus(MA) and data bus(MD) and the switching unit(120).
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