| 摘要 |
PURPOSE: A PCI apparatus having a cache function is provided to minimize a standby time of a response with respect to an access of a PCI bus for thereby enhancing a performance of an entire system by providing a caching function so that a PCI is not occupied for long time in a system which uses a slow access time. CONSTITUTION: A PCI interface controller(PCIIFC)(10) includes a configuration register(11), an address decoder(12), a transfer type comparator(13), and a PCI stage machine(14). An address comparator(ADEC)(12) analyzes an address driven in an address phase of a PCI bus cycle and checks whether a memory connected with the CTU is accessed. A local cache control module(LCCM)(20) includes local cache memories(22, 23) in the CTU, an LCC(21) for controlling the cache memory, a PCI address buffer(ADDBUF)(25) for storing an address from the PCI address buffer, and a data buffer(260 for storing the PCI write data. A TAG memory(23) stores an address by the direct cache address mapping method for checking whether the cache data memory(22) has the data with respect to the read cycle performed in the PCI. The LCC(21) generates a signal for controlling the ADDBUF(25) and signals(206, 207) for controlling the WDBUF(26). The ADDBUF(25) is a buffer capable of storing the address of the cycle which is performed through the PCI bus.
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