| 摘要 |
PURPOSE: A semiconductor device for setting-up a test mode is provided to prevent an SDRAM(Synchronous DRAM) from setting-up at an undesirable test mode by a user. CONSTITUTION: A command decoder(10) receives external signals of CLK(clock), RASB(Row Address Strobe Bar), CASB(Column Address Strobe Bar), CSB(Chip Select Bar), WEB(Write Enable Bar), and A<7> to decode the same. A shift register(11) stores a TMA<1:m >address of "0" bit during m clocks when the CSB signal has a "row" value during at least m clocks. A logic(12) receives a PTRS(Pretest Resistor Setup) signal when the A<7> signal inputted to the command decoder(10) and the CSB, RASB, CASB, and WEB signals represent a fixed logic value. A test register(13) stores a logic value of TDA<i:j>(Test Decoding Address i-j) with k bits according to a TRS(Test Register setup) signal outputted from the logic(12) which receives the PTRS signal when the address of the shift register(11) is a desirable address. A test decoder(14) outputs a test mode signal.
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