| 摘要 |
PURPOSE: A multiple arithmetic unit by using a bypass bus is provided to increase the number of operands which may be simultaneously used by using the number of input/output terminals of predetermined register files. CONSTITUTION: A multiple arithmetic unit has a first external operand bus(OP1), a second external operand bus(OP2), a first external bypass bus(BYP1), a bus distributer(50) to distribute a second external bypass bus(BYP2) received from the different multiple arithmetic unit, an adder/subtracter(63), a logical AND arithmetic unit(64), a logical OR arithmetic unit(65), a logical exclusive OR arithmetic unit(66), an address computing unit(67), a shifter(68), a bus control unit(69) for outputting an arithmetic result received from a detail arithmetic unit to a result output bus(RES1) and the first external bypass bus(BYP1) according to a control signal(control_bc) and a multiple multiplexer(51¯62). The multiple multiplexer(51¯62) selects a specified buses among the first external operand bus(OP1), the second external operand bus(OP2), the first external bypass bus(BYP1) and the second external bypass bus(BYP2) distributed from the bus distributer(50) according to a multiple operand bus selecting signal(C1¯C12) to the operand bus of the detail arithmetic unit.
|
