AREA-EFFICIENT VARIABLE LENGTH CODEC APPARATUS

摘要

PURPOSE: A variable length codec apparatus is provided to be capable of coding symbols inputted from the outside into variable length codewords via bit serial processing or decoding variable length codewords inputted from the outside. CONSTITUTION: A variable length codec apparatus includes an address generator(100) for sequentially generating address data(ADi) from a codebook memory(200) and a mask memory(300). The codebook memory(200) generates the first store codeword(Cij) corresponding to the address data(ADi) in response to the address data (ADi) inputted from the address generator(100). The mask memory(300) stores determination bit columns at the same address(ADi) to the address(ADi). A matching processor(400) logically calculates the first store codeword of the j-th address from the codebook memory(200) and the second store codeword of the j-th address from the mask memory(300) to generate the first and second match signals(qij, CMij), respectively. An index generator(500) generates an address signal(In) corresponding to the first matching signal(qij) from the matching processor(400) in response to the boundary detection signal(fj) from a boundary detection unit(600). The boundary detection unit(600) generates a given boundary detection signal(fj) based on the second match signal(CMij) from the matching processor(400). A decoding memory(700) outputs the codeword(FCW) stored as the address signal(In) in response to the address signal(In) from the index generator(500). The first multiplex(800) provides only the j-th bit in the first store codeword(Cij) of the N bit from the codebook memory(200). The second multiplex(900) detects only the j-th bit in the second store codeword from the mask memory(300). The packing unit(1000) determines whether the j-th bit(Psij) in the first store codeword(Cij) from the first multiplex(800) in response to a determination signal(Vsij) from the second multiplex(900).