| 摘要 |
PURPOSE: A clock frequency controlling device is provided to be capable of changing a clock frequency without synchronous loss using a plurality of phase locked loops. CONSTITUTION: A clock frequency controlling device comprises a phase locked loop controller(20), a multiplexer(30), and first and second phase locked loops(40,50). Each of the first and second phase locked loops(40,50) generates a clock synchronized with an internal clock. The phase locked loop controller(20) receives output signals of the first and second phase locked loops(40,50), and controls the first and second phase locked loops(40,50). The phase locked loop controller(20) outputs a select signal(mx_select) according to an inputted frequency change signal(freq_cnt). The multiplexer(30) receives output signals of the first and second phase locked loops(40,50) to select either one of the received output signals according to the select signal(mx_select).
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