| 摘要 |
PURPOSE: DLL and PLL connected to a synchronous delay circuit are provided to increase a precision degree of a locking range by generating an internal clock phase-synchronized to an external clock. CONSTITUTION: A synchronous delay circuit outputs a synchronous clock synchronized to an external clock. A PLL generates an internal clock synchronized to the external clock by receiving an output clock of the synchronous delay circuit. The synchronous delay circuit includes a block buffer for generating a first clock delayed by the first delay time. A first dummy delay part(122) receives the first clock, and outputs a second clock that the first clock is delayed by the second delay time. A clock delay comparator(114) generates a third clock delayed by the third delay time, and generates a control signal and a flag signal when the first clock and the third clock are in a synchronous range. The phase delay circuit includes a second clock delay part, a clock driver, an oscillator and a phase/frequency detector.
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