| 摘要 |
PURPOSE: A buffer circuit is provided to be capable of minimizing switching delay of an output signal. CONSTITUTION: A buffer circuit comprises first to third PMOS transistors(P3,P4,P5) and two NMOS transistors(N1,N2). The current paths of the transistors(P3,N1) are formed in series between a power supply voltage(VCC) and a ground voltage(VSS), and the gates thereof are connected to receive a reference voltage(Vref) and an input signal(IN), respectively. The current paths of the transistors(P4,N2) are formed in series between the power supply voltage(VCC) and the ground voltage(VSS). The transistors(N1,N2) form a current mirror. The current path of the PMOS transistor(P5) is formed in parallel with that of the transistor(N2), and the gate thereof is connected to a substrate voltage(VBB).
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