发明名称 A METHOD AND STRUCTURE FOR PERFORMING INTEGRATED CIRCUIT WAFER TESTING AND ASSEMBLY
摘要 Methods for (a) testing an integrated circuit wafers and (b) creating integrated circuit dice assemblies using wafers are taught herein. Two integrated circuit wafers (1,2) are directly attached together using conductive bumps bonds (8), unlike other proposed methods that use a plurality of test dice and/or intermediate connection layers. The wafers are designed with matching glass openings (7) and bump bond pads (5) to provide a large number of connections between the wafers that have low resistance, capacitance and inductance. For testing purposes, one of the wafers (2), referred to herein as the test wafer, can be designed with embedded test circuitry that can be used to simultaneously test one or more of the integrated circuit designs on the second wafer (1), referred to herein as product wafer number one. The test wafer can be coupled to an external tester using either probes (3), conductive leads or bump bonds. After testing, the wafers are detached and the bump bonds are reflown for subsequent assembly. For assembly purposes, the same method can be used in which the test wafer is replaced with a second product wafer, referred to herein as product wafer number two. The two product wafers can hame different circuits and possibly different semiconductor processing technologies. Unlike other proposed methods, the product wafers are directly connected to one another with bump bond and require no intermediate connection layer. The product wafers are then cut into dice assemblies (12). Unused sections of the product wafers (13) are discarded. Unlike other proposed methods, this allows a large number of die assemblies to be created simultaneously without precision handling of individual dice. The resulting dice assemblies contain dice (6,9), one or more from each wafer, that are connected by the bump bonds. The dice assemblies can then be connected to external circuits using bump bonds (10) or conductive leads. In a modified assembly method, product wafer number one is first cut into dice which are then attached to product wafer number two. This modification provides higher yield in dice assemblies by selecting known good die. The disadvantage is more complex assembly using dice instead of only full wafers.
申请公布号 CA2268572(A1) 申请公布日期 2000.10.12
申请号 CA19992268572 申请日期 1999.04.12
申请人 MASON, RALPH DICKSON 发明人 MASON, RALPH DICKSON
分类号 G01R1/073;(IPC1-7):G01R31/26;H01L21/50 主分类号 G01R1/073
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