| 摘要 |
<p>A data processing arrangement (1) comprises a first processor (PROC1) for providing successive sets of input data, a second processor (PROC2) for receiving successive sets of output data and a memory system (2) comprising a plurality of memory circuits (MEM) for storing the input and output data. According to the invention, the data processing arrangement also comprises a master controller (MCP) for setting up the memory system by means of control commands (CC) associated with a set of input data and a set of output data. These control commands are received in the memory system by a control unit (MCU). When data (Di) from the set of input data is provided by the first processor, this control unit selects, on the basis of the control commands, a first memory circuit and generates a write address (AD_W) in said first memory circuit. In the same way, when data (Do) from the set of output data is required by the second processor, the control unit, on the basis of the control commands, selects a second memory circuit and generates a read address (AD_R) in said second memory circuit. Thus, there is no need for the processors to provide addresses when they require or send data; so that a simple data processing arrangement is achieved.</p> |
