| 摘要 |
PURPOSE: A method for manufacturing a semiconductor memory device is provided to increase the margin of forming a buried contact as well as a direct contact structure. CONSTITUTION: The method includes following steps. At the first step, a gate electrode of a transistor whose surface is blocked by an upper insulator layer is formed on a predetermined region of the semiconductor substrate(21) which is divided into a memory cell region and a peripheral region by a field oxide layer(22). The first insulator layer(26) is formed on the result of the first step, the first insulator on the memory cell region is etched back, and the first spacer which is coupled with the upper insulator layer is formed on the sidewall of the gate electrode. At the third step, a pad polysilicon layer is accumulated on the result of the preceding steps, the pad polysilicon layer is flattened by etching the upper insulator layer, and a contact pad is formed by removing selectively the pad polysilicon layer formed on the region outside of the direct contact or the buried contact of the memory cell region by using photo etching process. At the forth step, the second insulator layer is formed on the result and the second spacer which is coupled with the upper insulator layer is formed on the gate electrode sidewall on the peripheral regions(27) by etching back the second insulator layer and the first insulator layer on the peripheral region exclusive of the memory cell region. At the fifth step, the second insulator layer on the direct contact region of the memory cell region and the contact pad corresponding to the direct contact region is exposed. At the sixth step, the first conductive layer which is coupled with the contact pad corresponding to the direct pad region is formed and patterned with a bit line pattern. At the seventh step, the third insulator layer is accumulated, a flattening layer is accumulated on the third insulator layer and the result is polished. At the eighth step, the flatten layer on the buried contact region is selectively removed to expose the contact pad. At the last step, the second conductive layer is accumulated and is patterned with a capacitor storage electrode pattern.
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