发明名称 |
Multiple function processor for communication signals |
摘要 |
<p>An apparatus for processing digital signals includes a multiplier having a first input and a second input and an output producing a product. An adder is connected to receive the product from the multiplier as a first input to produce a sum. A first register is connected to receive and store the sum and to provide a second input to the adder in response to a clock signal. A second register is connected to receive and store the output of the first register in response to an inverse of the clock signal to enable the addition of two products in a single clock cycle. <IMAGE></p> |
申请公布号 |
EP1043653(A2) |
申请公布日期 |
2000.10.11 |
申请号 |
EP20000106703 |
申请日期 |
2000.03.29 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
BAO, JAY |
分类号 |
G06F7/00;G06F7/544;H04J11/00;H04L27/00;H04N5/40;(IPC1-7):G06F7/544 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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