Integrated cache memory with system control logic and adaptation of RAM bus to a cache pinout

摘要

An integrated circuit and computer system. According to one embodiment of the present invention an integrated circuit on a single substrate for use with a microprocessor which is coupled to a processor bus is provided, and the integrated circuit includes a cache random access memory array and a data path logic control unit, such as multiplexer which is coupled to the cache random access memory array and has an output for coupling to the processor bus. In one embodiment, a further multiplexer having an output for coupling to a first portion of a memory is provided, and this multiplexer further has input for coupling to a second portion of the memory bus. The IC according the present invention is also for use with a second IC which includes control logic for controlling system memory and for controlling the processor bus and memory bus as well as interfacing to other buses such as peripheral bus. The present invention also provides for improved layout of a cache array with a data path logic management unit as well as power management features for the cache array and a tag RAM with comparator on, in one embodiment, the same chip with the cache array or on an associated chip in another embodiment.