Clean process for manufacturing of split-gate flash memory device having floating gate electrode with sharp peak

摘要

The following steps are used to form a split gate electrode MOS FET device. Form a tunnel oxide layer over a semiconductor substrate. Over the tunnel oxide layer, form a doped first polysilicon layer with a top surface upon which a native oxide forms. Then as an option, remove the native oxide layer. On the top surface of the first polysilicon layer, form a silicon nitride layer and etch the silicon nitride layer to form it into a cell-defining layer. Form a polysilicon oxide dielectric cap over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, etch the first polysilicon layer and the tunnel oxide layer to form a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Form spacers on the sidewalls of the gate electrode stack. Then form blanket inter-polysilicon dielectric and blanket control gate layers covering exposed portions of the substrate and covering the stack. Pattern the inter-polysilicon dielectric and control gate layers into a split gate electrode pair. Form a source region self-aligned with the floating gate electrode stack; perform a tungsten silicide anneal; and form a drain region self-aligned with the control gate electrodes.