发明名称 Programmable function block
摘要 A programmable function block 20 comprises a logic block 21 including a full adder 31 and at least one preposition logic 32, and an input block 22 including programmable input switch units 40-1 through 40-9 for use in selectively switching a HIGH logic level signal, a LOW logic level signal, and a signal on interconnection lines 50. The preposition logic 32 comprises an exclusive OR circuit 32-1 and a multiplexer 32-2 and functions as various different logic circuits by means of setting some of the inputs thereof to a HIGH logic level or a LOW logic level. Thus, the logic block functions as various different logic circuits depending on the state of the inputs. In addition, the full adder provides fast arithmetic operation.
申请公布号 US6130553(A) 申请公布日期 2000.10.10
申请号 US19980169948 申请日期 1998.10.13
申请人 NEC CORPORATION;REAL WORLD COMPUTING PARTNERSHIP 发明人 NAKAYA, SHOGO
分类号 H03K19/173;H03K19/177;(IPC1-7):G06F7/38 主分类号 H03K19/173
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