发明名称 ERROR CORRECTION DECODER
摘要 PROBLEM TO BE SOLVED: To reduce a circuit scale of an error correction decoder by decreasing a capacity of a memory without deteriorating decoding arithmetic precision in the case of decoding turbo code. SOLUTION: The error correction decoder has 1st-3rd memories 3-5 that store ya, yb, yc resulting from separating turbo code received data (y) by an S/P conversion section 2, 4th and 5th memories 12, 13 that store a result of backward probability calculated earlier by a 1st D (transition probability) calculation section 9 and a B (backward probability) calculation section 11, a 6th memory 7 that stores preceding reliability information, a 7th memory 21 that stores this reliability information and decoded data, an L (combined probability) calculation section 16 that obtains a combined probability on the basis of the forward probability and the backward probability by a 2nd D calculation section 10 and an A (forward probability) calculation section 15, an L(u) calculation section 17 that calculates decoded data, an Le(u) calculation section 18 that calculates reliability information and a MAP control section (repetitive control section) 25.
申请公布号 JP2000278144(A) 申请公布日期 2000.10.06
申请号 JP19990076761 申请日期 1999.03.19
申请人 FUJITSU LTD 发明人 IBA HIDEO;OBUCHI KAZUCHIKA
分类号 G06F11/10;H03M13/00;H03M13/23;H03M13/27;H03M13/29;H03M13/39;H03M13/45;H04L1/00;(IPC1-7):H03M13/23 主分类号 G06F11/10
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