发明名称 NON-VOLATILE SEMICONDUCTOR MEMORY AND ERASING METHOD FOR ITS STORAGE DATA
摘要 <p>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory in which distribution of threshold values is made narrow, operation speed is increased, operation voltage is made low, and which is suitable for a memory cell. SOLUTION: In a non-volatile semiconductor memory consisting of memory cells M01-M32, bit lines BL0-BLn connected to drains of cells, word lines W0-Wn connected to control gates of cells, cell source lines 1 connected to sources of cells, reference cells MR provided corresponding to cells. and a sense amplifier 3 comparing a current Im of a selected bit line with a reference current Ir, a cell well line 2 connected to a well of a cell is provided, in order to make distribution of threshold values of cells after erasing data the prescribed distribution, when a cell of a low threshold value being over-erased is detected, the prescribed bias voltage is applied to a cell source line 1, while a potential of a cell well line is made equal to a potential of the cell source line 1, and a cell of a low threshold value is detected by comparing the Im with the Ir.</p>
申请公布号 JP2000276882(A) 申请公布日期 2000.10.06
申请号 JP19990078411 申请日期 1999.03.23
申请人 NEC CORP 发明人 WATANABE KAZUCHIKA
分类号 G11C16/02;G11C16/34;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C16/02;H01L21/824 主分类号 G11C16/02
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