| 摘要 |
PROBLEM TO BE SOLVED: To provide a novel differential coding circuit reduced in time delay. SOLUTION: This differential coding circuit 100 comprising a 1-bit 2-stage serial parallel conversion circuit 110, a two-digit binary adder 130, N-stage delay registers 141, 142, and exclusive OR circuits 120, 150 can conduct differential coding with time delays of the N-stage delay registers 141, 142 only. In the case the exclusive OR circuit 150 is placed to each stage of the N-stage delay registers 141, 142, a differential code consisting of a parallel signal can be outputted.
|
