| 摘要 |
PROBLEM TO BE SOLVED: To realize an interruption processor loaded with information such as the sort of interruption generation, the ID of an informing source CPU and the ID of an informed CPU and capable of quickly executing interruption processing and to realize also an interruption informing method. SOLUTION: The interruption processor is provided with a command decoder 9 which is connected between a system bus 5 and an I/O bus 8 and which is capable of decoding a transaction meaning an interruption and an interruption receiving part 10 for interpreting and processing a normal transaction received from the I/O bus 8 as an I/O interruption, and the processor is constituted so as to process the normal transaction from the I/O bus 8 equally to the processing of interruption information from a normal interruption line. Since interruption information can be processed as an interruption transaction, performance deterioration generated when plural I/O devices 6, 7 are simultaneously driven due to low interruption resolution and the processing of interruption order when plural DMAs are simultaneously generated can be improved. Thereby interruption processing can be quickly execute.
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