发明名称 DUTY COMPENSATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a duty compensating circuit in which a duty cycle can be set so as to be 50%. SOLUTION: A differentiation circuit 2 converts an input signal from an input terminal 1 into a pulse signal. A variable delay circuit 3 delays the pulse signal, and outputs a delay signal. A latch circuit 4 controls an output signal to be risen according to the input of the pulse signal, and fallen according to the input of the delay signal. A reference signal generating circuit 6 outputs a reference signal based on a complementary signal obtained by inverting the output signal from the latch circuit 4 and a control signal from a control circuit 7. The control circuit 7 supplies the control signal for controlling delay amounts to be delayed in the variable delay circuit 3 according to the pulse signal from the differentiation circuit 2 and the reference signal from the reference signal generating circuit 6 to the variable delay circuit 3 and the reference signal generating circuit 6. Thus, the delay time of the variable delay circuit 3 is delayed only for a cycle, and the rising is generated from the half delay time so that a duty cycle can be set so as to be 50%.
申请公布号 JP2000278100(A) 申请公布日期 2000.10.06
申请号 JP19990085662 申请日期 1999.03.29
申请人 NEC CORP 发明人 YAMAGUCHI HIROSHI
分类号 H03K5/04;H03K5/13;H03K5/131 主分类号 H03K5/04
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