发明名称 A/D CONVERTER
摘要 PROBLEM TO BE SOLVED: To remarkably shorten test time by sampling an analog signal at a cyclic interval, holding it during conversion, holding a potential difference between a low-order reference voltage and an operating point voltage, operating high-order and low-order expected value codes to be set to a built-in reference voltage generating circuit (DAC) on the basis of the measured result of a comparative measuring means and temporarily storing these codes. SOLUTION: A sequential comparative register value is changed on the basis of a comparator output signal Vout outputted from a one-bit comparator circuit 20. Thus, the output voltages of a high-order DAC output voltage VDA and a low-order DAC output voltage VLSB1 respectively generated out by a DAC 10 are independently controlled. Further, the one-bit comparator circuit 20 has the circuit configuration of respectively feeding back and connecting the high- order DAC output voltage VDA and the low-order DAC output voltage VLSB1. Expected value data outputted from an expected value register circuit 60 are inputted to a sequential comparative register circuit 30.
申请公布号 JP2000278133(A) 申请公布日期 2000.10.06
申请号 JP19990076401 申请日期 1999.03.19
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 MASUDA YOSHINOBU
分类号 H03M1/12;H03M1/38;(IPC1-7):H03M1/38 主分类号 H03M1/12
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