| 摘要 |
PROBLEM TO BE SOLVED: To lower the use rate of a system bus by attaching a property indicating cashe memory residence to a memory read instruction and performing control for expelling the oldest block between corresponding sets. SOLUTION: A selector part 20 selects a data array part 25-1 or data array part 25-2 as a set at cache hit time. The data of the selected set are stored in a data register 21, transmitted through a data bus 28, and passed to a processor 11 through the data bus 28. The oldest set between sets in a cache memory 13 is selected and determined by an LRU control part 22 and a cache memory expelling control part 23 controls the expelling of the determined set from the cache memory 13.
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