| 摘要 |
The device includes a programable address memories (5,6), test circuits (7,8) for (at the test phase) calculating the parity of each row and column, comparing the calculated and expected parity for each row and column, and a correction circuit. In the normal mode inversion of the value in the cell is arranged by identifying the row and column marked in the address memory. The address comprises a marked column and a marked row associated with those in the matrix, a test circuit marking a row and column valid. A flag is inserted in the cell in the same row of the column being marked and a flag in the cell of the same column of the row being marked.
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