NON-VOLATILE SEMICONDUCTOR MEMORY, AND METHODS FOR VERIFYING AND READING NON-VOLATILE SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To reduce a circuit scale by setting a word line voltage to plural steps according to a threshold voltage distribution at verifying operation, controlling a bit line so that it is pre-charged or not pre-charged according to a latch circuit data, detecting whether or not a threshold value of a memory cell exceeds a word line voltage, and defining the latch circuit according to the detected output. SOLUTION: This non-volatile semiconductor memory is comprised of a memory cell array 21, a bit line voltage generating circuit 22, and a read/verify control circuit 23. Verify-read operation is performed by sequentially lowering the voltages of word lines WL0-WL15. By making one of the voltages VB0-VB2 to the power source voltage and the others to the ground level, controlling NMOS transistor n3-n8 according to write data held by latch circuits LQ2, LQ1, and making a charging current flow to bit lines BL0, BL1 from one of the voltages VB0-VB2, the other write data are made off the object for verification.