发明名称 PHASE-LOCKED LOOP CIRCUIT AND DATA TRANSMITTER PROVIDED WITH THE SAME
摘要 PROBLEM TO BE SOLVED: To synchronize a master station and a slave station by detecting a phase difference between an input signal and an internal signal, relatively reducing the control power of phase synchronization when this value is within a first range or relatively making the control power about middle when this value exceeds the range and further performing phase synchronizing control while relatively enlarging the control power of phase synchronization when the value is within a larger range. SOLUTION: On the input side of a timing extracting part, plural taps are provided and an inputted demodulating signal is delayed just for the number of tap stages. The tap output or demodulating signal is respectively inputted to a BPF, the outputs of adjacent BPF are supplied to respective averaging parts 1-3 and the BPF outputs are averaged. Thus, since two symbols of BPF outputs are averaged, a noise signal contained in the demodulating signal can be reduced. The outputs of the respective averaging parts l-3 are supplied to an output selector circuit. Besides, the outputs of the respective averaging parts are supplied to a square circuit.
申请公布号 JP2000278125(A) 申请公布日期 2000.10.06
申请号 JP19990085933 申请日期 1999.03.29
申请人 FUJITSU LTD 发明人 KAKO TAKASHI;MIYAZAWA HIDEO
分类号 H03L7/107;H03L7/093;H04L7/033 主分类号 H03L7/107
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