发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To provide design equipment for a master slice type semiconductor integrated circuit which enables effective automatic wiring by arranging circuit elements, in which irregularity of characteristic of resistance elements is restrained. SOLUTION: As a means of assigning circuit elements to base elements on a master slice, element constitution priority assignment (S302) which tries assignment on the basis of a given element constitution method and automatic element selection assignment (S304) which tries assignment to the base elements, wherein the wiring length is shorter than the connection relation between circuit elements are installed. The respective assignment results are evaluated (S305), and assignment whose evaluation value becomes higher is adopted. Until assignment for all circuit elements is finished, processes S302-S307 up to S308 are repeated.
申请公布号 JP2000277714(A) 申请公布日期 2000.10.06
申请号 JP19990085810 申请日期 1999.03.29
申请人 MATSUSHITA ELECTRONICS INDUSTRY CORP 发明人 KONISHI SHIGEAKI;MITSUYASU HIROKO;MISHIMA HIDEKI;KUMASHIRO SHINICHI
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118;(IPC1-7):H01L27/118 主分类号 H01L21/822
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