PULSE CLOCK/SIGNAL DELAY APPARATUS AND METHOD

摘要

A Pulse Clock Delay (PCD) apparatus (208) includes a selectable plurality (N d) of series-connected pulse transition delay units (209) from a total pluralit y (Nmax) of such units. Each unit provides an incremental transition delay interval .DELTA.~t?. The PCD may be connected to a first intermediate proxim al node (nla) and an adjacent electrically isolated second intermediate node (nlb) where the first and second intermediate nodes are in a shorter (215a, 215b) of two signal paths having respective proximal and spaced apart distal ends (212, 216) in an electrical network. Control means (205), responsive to the difference in electrical length between the two signal paths (214, 215), configures the switchable selection means to select a particular number of delay segments such that the propagation of a first edge transition (102) through the series combination of the shorter first path (215a, 215b) and th e delay segment (208) is delayed sufficiently to arrive at the second path distal end (216) within +/-.DELTA.~t? of the time of arrival of the first ed ge transition propagating through the second path. Multiple PCD~s? may be distributed on a PCB to compensate delay differences for multiple pairs of unequal length bifurcated clock/signal lines.