| 摘要 |
<p>A barrier layer 4, an Al or Al alloy interconnect metal layer 5, a Ti layer 2, and a TiN anti-reflection layer 3 are formed on an insulating layer formed over a semiconductor substrate surface. Subsequently, the Ti layer 2 (at least) is patterned before the structure is heated in order to form a TiAl alloy layer 8. An interlevel dielectric is deposited and planarised and another heating step is performed to degas the interlevel dielectric. Patterning a Ti layer rather than a TiAl alloy layer reduces etching residue, and the presence of the TiAl alloy layer reduces void formation in the Al layer 5 when the interlevel dielectric is heated in the degassing step.</p> |
