发明名称 |
Fault-tolerant multiple processor system with signature voting |
摘要 |
A multiprocessor computer system and associated method having processing error detection capability is disclosed for error-free processing of an instruction set. The instruction set is replicated and processed substantially in parallel through a plurality of processing nodes of the computer system. Each processing node collects a compressed hardware signature commensurate with and derived from the execution of the instruction set. Subsequent instruction set processing, the collected hardware signatures from each processing node are compared and the presence or absence of a processing error is determined with reference to a predetermined voting scheme. Processing of the instruction sets through the plurality of processing nodes is typically asynchronous with synchronization occurring subsequent each processor's execution of the instruction set, such that each processor can be driven by an independent clock.
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申请公布号 |
US6128755(A) |
申请公布日期 |
2000.10.03 |
申请号 |
US19940295493 |
申请日期 |
1994.08.25 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BELLO, STEPHEN EDWARD;HUA, KIEN ANH;PEIR, JIH-KWON |
分类号 |
G06F11/18;G06F15/16;G06F15/177;(IPC1-7):G01R31/28 |
主分类号 |
G06F11/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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