发明名称
摘要 <p>PURPOSE:To simply attain line interpolation processing with a small capacity memory and a shift register by converting a signal corresponding to each horizontal scanning line in a unit picture block area and an interpolation signal of an interpolation horizontal scanning line sequentially into data. CONSTITUTION:A line interpolation section 11 is a circuit section implementing interpolation and simultaneous processing to a Y signal, a CR signal and a CB signal from a changeover switch 10, and 8-bit digital data 8 are shifted by a bit shift register and the result is fed to an adder. The adder adds output data and input data from the 8-bit shift register and a 1/2 multiplier multiplies the result of addition by 1/2 to obtain an averaging signal and it is outputted to an H terminal of the changeover switch. Furthermore, the input data are fed to an L terminal of the changeover switch and the supply data to both terminals are switched and outputted to a DCT section 12 based on a switching control signal. Then a signal corresponding to each horizontal scanning line in a unit picture block area an interpolation signal for an interpolated horizontal scanning line are in turn converted into data.</p>
申请公布号 JP3093004(B2) 申请公布日期 2000.10.03
申请号 JP19910296441 申请日期 1991.10.16
申请人 发明人
分类号 H04N7/01;H04N19/423;H04N19/426;H04N19/59;H04N19/60;H04N19/625;H04N19/85;(IPC1-7):H04N7/30 主分类号 H04N7/01
代理机构 代理人
主权项
地址