发明名称
摘要 <p>To avoid large consumption of current, a memory system includes a first memory cell array and a second memory cell array, each including a plurality of word lines connected to a plurality of memory cells of the first and second memory cell arrays, respectively, a first activator for activating a first word line of the word lines of the first memory cell array, and for making the first memory cell array output data from the memory cells connected to the first word line, a second activator for activating a second word line of the word lines of the second memory cell array, and for making the second memory cell array output data from the memory cells connected to the second word line, a first sense circuit for receiving the data from the first memory cell array, and for amplifying the data from the first memory cell array, a second sense cirsuit for receiving the data from the second memory cell array, and for amplifying the data from the second memory cell array at a rate faster than the first sense ciruit, and an output control circuit for outputting the data of the second sense circuit, and for outputting subsequently the data of the first sense circuit.</p>
申请公布号 JP3093632(B2) 申请公布日期 2000.10.03
申请号 JP19960105244 申请日期 1996.04.25
申请人 发明人
分类号 G11C11/41;G11C7/06;G11C7/10;G11C16/06;G11C17/00;(IPC1-7):G11C16/06 主分类号 G11C11/41
代理机构 代理人
主权项
地址