| 摘要 |
An output delay circuit has a counter which is reset at every input of an input signal of a first signal state thereto and counts input clocks while the input signal of a second signal state is inputted thereto; a comparator for comparing an accumulated number of the input clocks having been counted by the counter with a predetermined clock number set in advance; and a logic circuit for, when it is determined by the comparator that the accumulated number of the input clocks is less than the predetermined clock number, outputting an output signal having a signal state same as the first signal state of the input signal, while for, when it is determined by the comparator that the accumulated number of the input clocks is not less than the predetermined clock number, outputting an output signal having a signal state same as the second signal state of the input signal
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