| 摘要 |
In order to prevent an output offset voltage from occurring because of a relative difference of threshold voltage Vth between NMOS and PMOS in transmission of dc voltage, a semiconductor integrated circuit is constructed in a circuit configuration comprising a first depletion-mode N-channel MOS transistor and a first depletion-mode P-channel MOS transistor, a gate of each transistor being connected to an input terminal and a source of each transistor being connected to an output terminal, a second depletion-mode N-channel MOS transistor having W/L equal to that of the first depletion-mode P-channel MOS transistor, a drain of the transistor being connected to the output terminal and a gate and a source of the transistor being connected both to a lower-voltage-side power supply, and a second depletion-mode P-channel MOS transistor having W/L equal to that of the first depletion-mode P-channel MOS transistor, a drain of the transistor being connected to the output terminal and a gate and a source of the transistor being connected both to a higher-voltage-side power supply.
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