INSTRUCTION FETCH UNIT AND PROCESSOR PROCESSING METHOD

摘要

PURPOSE: A method and a system for processing an instruction patch are provided to minimize a delay time which occurs when an instruction cache accesses an external memory wherein a free fetch circuit fetches an instruction sequence which includes an instruction of a flow control instruction target address which is outputted based on a scan logic. CONSTITUTION: An instruction fetch system(120) fetches an instruction from an instruction memory(110) of an instruction cache system. The instruction fetch system(120) processes a flow control instruction like a conditional branch, sub-routine and return and provides an instruction and other flow control instructions to an instruction decoder(130). The instruction decoder(130) decodes an instruction to an incoming sequence from the instruction fetch system(120) and fills the entry of the decode buffer(140). A processor(100) includes a scheduler(150) by which a computation is performed form the decoder buffer(140) which executes the instruction to the data path(170). The instruction decoder(130) decodes one instruction for a cycle.