| 摘要 |
PURPOSE: A defect remedying circuit and its method are provided to make it possible to cope with a position alteration of a faulty cell and repair a defect memory cell even a packaged condition. CONSTITUTION: A built-in self test(BIST) circuit compares data written in the memory and data outputted from the memory at a BIST mode, and generates an error signal representing if there is a defect cell, and a BIST address. A repair enable signal generator stores the BIST address as a repair address at the BIST mode, responsive to the error signal; at a normal mode, compares a logic address outputted from a logic and the repair address and outputs a repair enable signal to be used in activating a redundancy circuit in the memory in case the logic address corresponds to the defect cell.
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