| 摘要 |
PURPOSE: A vector processor architecture of a scalable width is provided to perform or emulate a 64-byte computation using a 32-byte vector processor. CONSTITUTION: A vector processor(100) includes an IFU(Instruction Fetch Unit)(100), an instruction decoder(120), an emulation state machine(130), a register file(140), an execution data path(150), and an adder(160). The IFU(110) fetches an instruction from an instruction memory, and the instruction is decoded by the instruction decoder(120). The emulator(130) transfers an instruction from the decoder(120) to the register file(140) or amends the instruction. If the 32-byte mode is selected, the non-amended instruction selects a certain register and element from the register file(140). The execution unit(150) executes a logic/arithmetic computation with respect to the data. The data are stored into the register file(140) again or are stored in a double accuracy accumulator(160) for an additional process. If the 64-byte mode is selected, the emulator(130) generates a 64-byte instruction having two 32-byte instructions and amends the 32-byte instruction for selecting and computing the data from first and second 32-byte registers of the register file(140). |
