BENCH MARK TEST FOR CACHE MISS

摘要

PROBLEM TO BE SOLVED: To provide the method and device for reducing the power consumption of a programmable DSP exclusive for a radio telephone or control and improving the execution efficiency of DSP algorithm. SOLUTION: A DSP in a cache consistency circuit has variable instruction length, high code density and easy programming and its structure and a set of instructions are optimized so that DSP algorithm is executed at low power consumption and high efficiency. A cache 814 is formed in a mega-cell mounted on a single integrated circuit 800 to shorten instruction access time. A performance monitoring circuit 852 is included in the mega-cell to monitor a selected signal and collect bench mark phenomena. The circuit 852 can be inquired through a JTAG interface 850. The performance of an internal cache is determined by sending a cache miss signal 816 from the cache 814 to the circuit 852. The bench mark phenomena are collected during the execution of a window selected by a window circuit 824 in the mega-cell.