| 摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit that can test an internal circuit of a semiconductor chip mounted with a serial/parallel converter employing a PLL circuit without increasing the number of test purpose external input terminals. SOLUTION: In a test operation, a test circuit 16 generates a 3rd clock signal group with n-phase to be fed to a serial/parallel conversion circuit 14. In a usual operation, an n-phase 1st clock signal group generated from a PLL circuit 12 is used and in the test operation, the 3rd clock signal group with n-phase generated by the test circuit 16 is used, and either of them is fed to the serial/ parallel conversion circuit 14 as an n-phase 2nd clock signal group. |
