| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a clock noise preventing circuit that employs no passive component, such as an inductor and a capacitor for preventing noise in a clock pulse, and is suitable for large scale integration. SOLUTION: A clock edge circuit 5 detects the leading edge of an input clock RCK. A gate timing detection circuit 7 counts clock signals resulting from multiplying a frequency of a synchronization clock from the detected clock edge as a start point to detect a 1st gate time that is an n-% (100>n>50) of a period of the received clock RCK and a 2nd gate time that is 50% thereof. A gate circuit 6 is provided with a 1st flip-flop that is set by the detected clock edge and reset at the 1st gate time, a 2nd flip-flop that is set by the detected clock edge and reset at the 2nd gate time, a 1st gate circuit that ANDs outputs of the 1st and 2nd flip-flop circuits, and a 2nd gate circuit that blocks the 2nd flip-flop from being reset at a time, corresponding to (n-50)% time of the period of the received clock.</p> |
