发明名称 REDUNDANCY CIRCUIT OF SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To reduce the number of fuse sets in a chip while securing a high yield. SOLUTION: A semiconductor memory is provided with eight banks; bank0, bank1,... bank7 which are simultaneously accessed. Two fixed spare row decoders 14F and two mapping spare row decoders 14M are arranged in each bank. Two fixed fuse sets 15F are provided in each bank corresponding to the fixed spare row decoder 14F. For example, eight mapping fuse sets 15M are provided in a semiconductor memory independently of the number of mapping spare row decoders 14M. Mapping information deciding that which banks the mapping spare row decoder 14M corresponds to is stored in the mapping fuse set 15M.
申请公布号 JP2000268598(A) 申请公布日期 2000.09.29
申请号 JP19990074040 申请日期 1999.03.18
申请人 TOSHIBA CORP 发明人 NAGAI TAKESHI
分类号 H01L21/822;G11C5/00;G11C7/00;G11C11/34;G11C29/00;G11C29/04;H01L21/82;H01L27/04;(IPC1-7):G11C29/00 主分类号 H01L21/822
代理机构 代理人
主权项
地址