| 摘要 |
PROBLEM TO BE SOLVED: To provide a product sum operation device and an image processor which are rich in versatility and capable of arithmetically processing the large capacity of image data at high speed with a simple configuration. SOLUTION: This product sum operation device performs product sum operation while being composed of latch circuits 101 and 102 for latching input signals composed of plural multiplicand data arranged in X rows and Y columns (X and Y are integers), an SRAM115 for storing the said multiplicand data and outputting the stored multiplicand data to any specified latch circuit, first-in first-out (FIFO) memories 111 and 112 for successively latching the multiplicand data and successively outputting the latched multiplicand data, latch circuits 104-109 for latching the multiplicand data from the FIFO memories 111 and 112, multiplication circuits 118-126 for multiplying coefficients to the multiplicand data from the latch circuits 101-109 and an adder circuit 127 for adding the multiplicand data from the multiplicand circuits 118-126. |
