发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce a leak current of a current source transistor(TR) in a charge pump circuit of a PLL circuit. SOLUTION: A charge pump circuit of this PLL circuit that is activated by an UP signal or a DOWN signal generated by a phase lead or phase lag between a reference clock and a VCO output clock to produce a charging current or a discharge current to an LPF at the input of the VCO, consists of a current source transistor(TR) 12 that produces a charging current to the LPF, of a switching TR 11 that connects the current source TR 12 to a power supply in response to an UP signal, a current source TR 13 that produces a discharge current flowing from the LPF, and a switching TR 14 that connects the current source TR 13 to ground in response to a DOWN signal. Furthermore, a back gate bias is given to the current source TRs 12, 13 when the charge pump circuit is deactivated.
申请公布号 JP2000269808(A) 申请公布日期 2000.09.29
申请号 JP19990068881 申请日期 1999.03.15
申请人 NEC CORP 发明人 HASEGAWA ATSUSHI
分类号 H03L7/093;H02M3/07;H03L7/089;H03L7/18 主分类号 H03L7/093
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