| 摘要 |
PROBLEM TO BE SOLVED: To effectively use the interiors of trench regions for a wiring, to contrive reduction in a chip size, to reduce the size of a cell pattern in the direction intersecting orthogonally a word line in the case where a semiconductor device is applied to the memory cell of a CMOS STRAM, and to enable the speedup of the STRAM in the device using a trench element isolation structure. SOLUTION: When trenches are formed on a semiconductor substrate 10 for selectively forming a plurality of trench isolation regions on the substrate 10, and an insulator 16 is buried in the trenches in the manufacturing method of a semiconductor device, the manufacturing method is provided with a first process for forming a cavity 17 on the insulator which is buried in the interior of at least the trench on one side of the trenches, a second process for opening a plurality of holes connected with the cavity 17 in the insulator, and a third process for burrying the insulator in the holes and the interior of the cavity 17. |
