发明名称 SEAMLESS MULTIPLEXER
摘要 <p>PROBLEM TO BE SOLVED: To decrease delays caused in a processing stage from an input time unitl a multiplexing processing time and to minimize accumulated errors caused when replacing time referencing information. SOLUTION: A signal system conversion circuit 11 selectively converts a TS signal of an M system into a TS signal of a required N system, a multiplexer circuit 12 multiplexes the converted TS signal on a TS signal, a PCR extract circuit 13 extracts a packet including a PCR denoting a reference time required to configure a program from the TS signal of the M system, a PCR reproducing circuit 14 rewrites contents of the PCR in this packet into contents, to which the time required for signal conversion processing by the signal system conversion circuit 11 is added, and the multiplexer circuit 12 multiplexes the rewritten contents on the TS signal.</p>
申请公布号 JP2000269906(A) 申请公布日期 2000.09.29
申请号 JP19990068191 申请日期 1999.03.15
申请人 TOSHIBA CORP 发明人 OZEKI KAZUO;SASAKI NOBUYUKI
分类号 H04J3/00;H04L12/70;H04N7/24;H04N19/00;H04N19/42;H04N19/423;H04N19/70;H04N19/85;(IPC1-7):H04J3/00;H04L12/56 主分类号 H04J3/00
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