| 摘要 |
PROBLEM TO BE SOLVED: To improve the use efficiency of a cache memory by providing a control circuit which determines an expellant entry according to priority level information among memory access kinds, access history information, and memory access information showing the kind of memory access. SOLUTION: The control circuit determines the expellant entry according to the priority level information among memory access kinds, access history information, and memory access information showing the kind of access. For example, a cache 10 has a memory cell part composed of an access kind data array 14, etc., a hit/miss decision circuit, an expelled object WAY determining circuit 16, an non-expelled-object WAY determining circuit 17, and an LRU/ access kind array control circuit 18. The access kind data array 14 holds memory access kind information on data stored in respective WAYs of respective blocks at the time of a cache miss by the WAYs.
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